1. Field of the Invention
The present invention relates to a method of designing a semiconductor apparatus and, particularly, to a method of designing a semiconductor apparatus in which a dummy line is placed in close proximity to a signal line.
2. Description of Related Art
Recent semiconductor apparatus include multilayered lines. The multilayered lines have a problem that a line of an upper layer is subject to breaking due to unevenness of a line of a lower layer. To address such a problem, there is a technique that equalizes the pattern density of an entire chip for each layer. This technique is disclosed in Japanese Unexamined Patent Application Publication No. 2003-140319 (Related art 1).
FIG. 7 schematically shows the layout of a semiconductor apparatus 100 according to the related art 1. As shown in FIG. 7, the semiconductor apparatus 100 includes a signal line 101 and a dummy line 102. According to the related art 1, if the pattern density in a given area does not reach a predetermined value, the dummy line 102 is placed in an area where the signal line 101 is not placed. The dummy line 102 has a prescribed line width. A space between signal lines is filled by the dummy line, thereby allowing a data rate within a mask to reach a predetermined value. It is therefore possible to equalize the surface of a line layer. Placing a dummy line which covers a large area enables reduction of a mask data amount.
On the other hand, as a manufacturing process of semiconductor apparatus has been moved to finer design rules, a distance between lines becomes shorter. A line is generally a metal line. If a distance between lines is short, capacitance coupling occurs between lines and parasitic capacitance increases accordingly. Further, if an area of a metal line is larger, parasitic capacitance increases accordingly. Thus, parasitic capacitance increases as a distance between adjacent metal lines is shorter and a total area of the metal lines is larger. Therefore, if a large dummy line is placed in close proximity to a signal line, parasitic capacitance of lines increases to cause larger signal transmission delay. To address this, a method of arranging dummy lines in consideration of capacitance coupling between lines and parasitic capacitance is disclosed in Japanese Unexamined Patent Application Publication No. 2000-277615 (Related art 2).
FIG. 8 shows a semiconductor apparatus 200 according to the related art 2. As shown in FIG. 8, the semiconductor apparatus 200 includes a signal line 201 and dummy lines 202 and 203. The dummy lines 202 and 203 are in the form of blocks that respectively have a predetermined area. The dummy line 202 has a small dummy line area, and the dummy line 203 has a large dummy line area. According to the related art 2, the dummy line 202 with a small dummy line area is placed in the area adjacent to the signal line 201, and the dummy line 203 with a large dummy line area is placed in the area not adjacent to the signal line 201. The dummy line which is adjacent to the signal line 201 is thereby small, which shortens a length where the signal line 201 and a dummy line are arranged in parallel. This prevents the occurrence of capacitance coupling between a signal line and a dummy line and reduces an increase in parasitic capacitance of a signal line.
However, the related art 2 has a problem that the number of patterns increases as the number of blocks increases. In the recent manufacturing process with finer design rules, optical proximity correction (OPC) is generally made for each of the patterns in a mask. Thus, if the number of patterns is large, it takes an enormous amount of time for the OPC process. Further, an increase in the number of patterns causes an increase in cost for mask production.
During a manufacturing process, a defect is attached randomly on semiconductor apparatus. In the recent manufacturing process with finer design rules, a signal line and a dummy line can be short-circuited due to the effect of such a defect or the like because a distance between the lines is short. If a signal line and a dummy line are short-circuited, an area of the signal line apparently increases, which causes an increase in parasitic capacitance of the signal line. This leads to an increase in signal transmission delay, causing malfunction of a semiconductor apparatus. Because the short-circuit which occurs due to a defect only causes an increase in parasitic capacitance of lines and does not cause any problem in logic operation, it is often unable to detect the defect in a delivery inspection process. The related arts 1 and 2 do not take the effect of such a defect into account. Therefore, upon the occurrence of short-circuit due to a defect, parasitic capacitance of a signal line increases and a signal delay occurs, which can cause malfunction of semiconductor apparatus.